1. Field of the Invention
The present invention relates to a method of planarizing insulating film of a semiconductor device, more particularly a method of planarizing an interlayer insulating film provided between successive metal wiring layers.
2. Related Art Statement
Recently, in the miniaturized semiconductor integrated circuit, wirings using polycrystalline silicon and aluminum alloy or the like are laminated through interlayer insulating film consisting of insulating substance, such as SiO.sub.2 or the like. This interlayer insulating film is formed on a semiconductor substrate having uneven surface, i.e., protrusions and depressions on a top surface thereof caused by providing wirings on an underlayer. In this case, the insulating film is mere deposited on the substrate having wirings, the surface of the insulating film also becomes uneven in the same manner as in the substrate having uneven surface, so that fine wiring can not be formed on the interlayer insulating film, if unevenness of the surface of the interlayer insulating film is not decreased by performing any planarization treatment.
In order to perform planarization treatment, a method of etching back the insulating film formed on the substrate having uneven surface by plasma etching or chemical mechanical polishing process (hereinafter referred to as CMP process) or the like has been developed. In order to carry out this method, a method is needed for forming an insulating film having high filling capability so as to fill between fine wirings with the insulating substance completely. To this end, formation of insulating film by a chemical vapor deposition (hereinafter refer to as CVD) process using organic silicon compound such as tetraethylorthosilicate (hereinafter referred to as TEOS) or the like as a raw material is utilized. Particularly, the feature that atmospheric pressure CVD process (hereinafter, referred to as AP CVD process) using TEOS and ozone as a raw material obtains very high filling capability has been disclosed in H. Kotani et. al. Technical Digest of International Electron Device Meeting, p. 669, 1989. There is, however, a problem that the obtained insulating film has a different deposition speed in accordance with undercoating dependency, that is, the material of undercoating. In order to remove the undercoating dependency, the feature that at first, an insulating film is deposited by a plasma CVD method, and then, another insulating film is deposited by AP CVD method using TEOS and ozone as a raw material, has also been disclosed in H. Kotani et al. Technical Digest of International Electron Device Meeting, p. 669, 1989. Moreover, a method of treating the surface of insulating film deposited by plasma CVD process with the plasma of N.sub.2 and/or NH.sub.3 has been disclosed in K. Fujino et. al. J. Electrochem. Soc., Vol. 139, No. 6, June, 1992, pp.1690-1692. A method that the substrate surface is treated with organic solvent such as ethanol or the like to improve the filling capability and the quality of the insulating film formed by CVD using organic silicon compound as a raw material has been disclosed in U.S. patent application Ser. No. 08/034,748. A method that the solvent of the insulating film substance or its precursor is applied on the substrate, and then heating treatment is performed with proper temperature, thereby forming an insulating film, that is to say, a spin on glass (hereinafter, referred to as SOG) process has been well known as a method of fabricating insulating film having superior filling capability. For example, a method of planarizing the surface of the insulating film by an etching back using SOG and plasma etching has been disclosed in U.S. Pat. No. 4,775,550.
In case of performing the etching back by using CMP process, as disclosed in U.S. Pat. No. 5,169,491, an etching stop has to use in order to overcome the problem of insufficient controllability of etching amount. A method of etching back borophosphosilicate glass (hereinafter, referred to as BPSG) film by using SiO.sub.2 film as an etching stop has been disclosed in U.S. Pat. No. 5,169,491 and S. Kishi et al., Technical Abstracts of the 1993 International Conference on Solid State Devices and Materials, Makuhari, 1993, pp. 189-191. A method of etching back SiO.sub.2 film by using Si.sub.3 N.sub.4 film as an etching stop has been disclosed in U.S. Pat. No. 4,944,836. A method of etching back SiO.sub.2 by using diamond-like carbon as an etching stop has been disclosed in U.S. Pat. No. 5,246,884. However, suitable material of etching stop for etching back with CMP process the insulating film formed by CVD using the above organic silicon compound as a raw material or the SOG process has not been disclosed in any reference.